1. Field of the Invention
The present invention relates to a display apparatus, and can be applied to, for example, a current-driven self-light-emitting display apparatus, such as an organic EL (Electro Luminescence) element. The present invention is configured in such a way that the gate voltage of a transistor for driving a light-emitting element is set to a fixed potential, variations in the light-emission luminance due to variations in the threshold voltage of the transistor are corrected, and the fixed potential is supplied from signal lines, thereby making it possible to reduce the number of scanning lines and the number of wiring patterns of fixed potentials used in comparison with a known case.
2. Description of the Related Art
Hitherto, regarding a display apparatus using an organic EL element, various contrivances have been proposed, for example, in U.S. Pat. No. 5,684,365 and Japanese Unexamined Patent Application Publication No. 8-234683.
FIG. 15 is a block diagram showing a so-called known active-matrix display apparatus using an organic EL element. In a display apparatus 1, a pixel unit 2 is formed in such a manner that pixels (PX) 3 are arranged in a matrix pattern. In the pixel unit 2, scanning lines SCN are provided in units of lines in a horizontal direction with respect to the pixels 3 arranged in a matrix pattern, and signal lines SIG are provided for each column in such a manner as to intersect the scanning lines SCN at right angles.
As shown in FIG. 16, each pixel 3 is formed of an organic EL element 8, which is a current-driven self-light-emitting element, and a driving circuit (hereinafter referred to as a “pixel circuit”) of the pixel 3, the driving circuit being used to drive the organic EL element 8.
In the pixel circuit, one end of a signal level holding capacitor C1 is held at a fixed potential, and the other end of the signal level holding capacitor C1 is connected to the signal line SIG via a transistor TR1 that is turned on/off in accordance with a writing signal WS. As a result, in the pixel circuit, the transistor TR1 is turned on in response to the rise of the writing signal WS. The other end potential of the signal level holding capacitor C1 is set to the signal level of the signal line SIG. The signal level of the signal line SIG is sampled at the other end of the signal level holding capacitor C1 and held by the signal level holding capacitor C1 at the timing at which the transistor TR1 is changed from an on state to an off state.
In the pixel circuit, the other end of the signal level holding capacitor C1 is connected to the gate of a P-channel transistor TR2, whose source is connected to a power supply Vcc, and the drain of the transistor TR2 is connected to the anode of the organic EL element 8. Here, in the pixel circuit, the transistor TR2 is set to always operate in a saturated area, with the result that the transistor TR2 constitutes a constant current circuit using a drain-source current Ids represented by the following equation:Ids=(½)×μ×(W/L)×Cox×(Vgs−Vth)2   (1)where Vgs is the gate-source voltage of the transistor TR2, μ is the mobility, W is the channel width, L is the channel length, Cox is gate capacitance, and Vth is the threshold voltage of the transistor TR2. As a result, each pixel circuit drives the organic EL element 8 on the basis of the driving current Ids corresponding to the signal level of the signal line SIG that is sampled and held by the signal level holding capacitor C1.
The display apparatus 1 causes a write scanning circuit (WSCN) 4A of a vertical driving circuit 4 to sequentially transfer a predetermined sampling pulse and to generate a writing signal WS that is a timing signal for instructing writing into each pixel 3. A horizontal selector (HSEL) 5A of a horizontal driving circuit 5 causes a predetermined sampling pulse to be sequentially transferred to generate a timing signal, and each signal line SIG is set to the signal level of the input signal S1 by using the timing signal as a reference. As a result, the display apparatus 1 sets the terminal voltage of the signal level holding capacitor C1 provided in each pixel unit 3 in accordance with an input signal S1 in point sequence or in line sequence, and an image represented by the input signal S1 is displayed.
Here, as shown in FIG. 17, in the organic EL element 8, current/voltage characteristics change over time through use such that it becomes difficult for electric current to flow. In FIG. 17, reference character L1 denotes the initial characteristics, and reference character L2 denotes the characteristics caused by changes over time. However, when the organic EL element 8 is to be driven by the P-channel transistor TR2 in the circuit configuration shown in FIG. 16, the transistor TR2 drives the organic EL element 8 in accordance with the gate-source voltage Vgs set in accordance with the signal level of the signal line SIG, making it possible to prevent luminance changes in each pixel due to changes over time of the current/voltage characteristics.
If all the transistors constituting the pixel circuit, the horizontal driving circuit, and the vertical driving circuit are formed by N-channel transistors, these circuits can be collectively fabricated on an insulating substrate, such as a glass substrate with an amorphous silicon process. Thus, the display apparatus can be made simply and easily.
However, as shown in FIG. 18, in contrast with FIG. 16, when each pixel 13 is formed by using an N-channel type for the transistor TR2 and a display apparatus 11 is formed by a pixel unit 12 using a pixel 13, as a result of the source of the transistor TR2 being connected to the organic EL element 8, changes in the current/voltage characteristics shown in FIG. 17 cause the gate-source voltage Vgs of the transistor TR2 to be changed. As a result, in this case, electric current flowing through the organic EL element 8 gradually decreases through use, and the luminance of each pixel gradually decreases. In the configuration shown in FIG. 18, the light-emission luminance varies among the pixels due to variations in the characteristics of the transistors TR2. Variations in the light-emission luminance disturb uniformity on the display screen and are perceived as variations and roughness on the display screen.
For this reason, as a contrivance for preventing such a decrease in the light-emission luminance due to changes over time of the organic EL element and such variations in the light-emission luminance due to variations in the characteristics, a configuration shown in FIG. 19 has been proposed.
Here, in a display apparatus 21 shown in FIG. 19, a pixel unit 22 is formed in such a manner that pixels 23 are arranged in a matrix pattern. In the pixel 23, one end of a signal level holding capacitor C1 is connected to the anode of the organic EL element 8, and the other end of the signal level holding capacitor C1 is connected to the signal line SIG via-the transistor TR1 that is turned on/off in accordance with the writing signal WS. As a result, in the pixel 23, the voltage at the other end of the signal level holding capacitor C1 is set to the signal level of the signal line SIG in accordance with the writing signal WS.
In the pixel 23, one end of the signal level holding capacitor C1 is connected to the source and the other end thereof is connected to the gate of the transistor TR2, and the drain of the transistor TR2 is connected to a power supply Vcc via a transistor TR3 that is turned on/off in accordance with a driving pulse signal DS. As a result, in pixel 23, the organic EL element 8 is driven by the transistor TR2 of a source follower circuit, in which the gate potential is set to the signal level of the signal line SIG. Here, Vcat is the cathode potential of the organic EL element 8. The driving pulse signal DS is a timing signal for controlling the light-emission period of each pixel 3, and is generated by a drive scanning circuit (DSCN) 24B by sequentially transferring a predetermined sampling pulse.
Furthermore, in the pixel 23, ends of the signal level holding capacitor C1 are connected to predetermined fixed potentials Vofs and Vss via transistors TR4 and TR5 that are turned on/off in accordance with control signals AZ1 and AZ2, respectively. The control signals AZ1 and AZ2 are timing signals that are generated by control signal generation circuits (AZ1 and AZ2) 24C and 24D, each being provided in the vertical driving circuit 24, by sequentially transferring a predetermined sampling pulse.
FIG. 20 is a timing chart of one pixel 23 in the display apparatus 21. In FIG. 20, a reference character of a transistor that is turned on/off in accordance with a corresponding signal is shown for each signal. As shown in FIG. 21, in a light-emission period T1 in which the organic EL element 8 emits light, in the pixel 23, signal levels of the writing signal WS and the control signals AZ1 and AZ2 (parts (A) and (B) of FIG. 20) are made to fall to set transistors TR1, TR4, and TR5 to an off state, and the signal level of the driving pulse signal DS (part (D) of FIG. 20) is made to rise to set the transistor TR3 to an on state.
As a result, in the pixel 23, a constant current circuit that varies with a gate-source voltage Vgs resulting from the potential difference across the ends of the signal level holding capacitor C1 is formed by the transistor TR2 and the signal level holding capacitor C1, and the organic EL element 8 is made to emit light in accordance with the drain-source current Ids determined by the gate-source voltage Vgs. Thus, a luminance decrease due to changes over time of the organic EL element 8 is prevented. The drain-source current Ids is represented by equation (1) described with reference to FIG. 16. In the following, transistors are shown using symbols of switches.
When the light-emission period T1 ends, the transistors TR4 and TR5 are set to an on state in pixel 23, during the subsequent period T2, as shown in FIG. 22. As a result, in the pixel circuit 23, the potential across the ends of the signal level holding capacitor C1 is set to predetermined fixed potentials Vofs and Vss (parts (E) and (F) of FIG. 20), and the drain-source current Ids flows from the transistor TR2 to the transistor TR5 in response to the gate-source voltage Vgs resulting from the potential difference Vofs−Vss of the fixed potentials Vofs and Vss. During the period T2, the fixed potentials Vofs and Vss are set so that the potential difference across the ends of the organic EL element 8 does not become greater than a threshold voltage Vthel of the organic EL element 8, the organic EL element 8 does not emit light, and the transistor TR2 operates in a saturated area.
Next, in the pixel 23, during the predetermined period T3, as shown in FIG. 23, the transistor TR5 is set to an off state. As a result, in the pixel 23, as indicated using the broken line in FIG. 23, the voltage at the side end of the transistor TR5 of the signal level holding capacitor C1 increases in accordance with the drain-source current Ids of the transistor TR2.
As shown in FIG. 24, for the organic EL element 8, an equivalent circuit is represented by a parallel circuit of a diode and a capacitor of capacitance Cel. As a result, as shown in FIG. 25, the source voltage Vs of the transistor TR2 increases gradually in the period T3 in accordance with the drain-source current Ids of the transistor TR2. As a result, in the pixel 23, the potential difference across the ends of the signal level holding capacitor C1 is set at the threshold voltage Vth of the transistor TR2, and the terminal voltage of the signal level holding capacitor C1 on the transistor TR5 side is set to a voltage Vofs−Vth such that the threshold voltage Vth of the transistor TR2 is subtracted from the fixed potential Vofs. In this state, the anode potential Vel of the organic EL element 8 is represented by Vel=Vofs−Vth. In the display apparatus 21, the fixed potential Vofs is set so that Vel≤Vcat+Vthel is reached, with the result that the organic EL element 8 does not emit light in the period T3.
Next, in the pixel 23, as shown in FIG. 26, the transistors TR3 and TR4 are sequentially set to an off state in the subsequent period T4. By setting the transistor TR3 to an off state earlier than the transistor TR4, it is possible to suppress variations in the gate voltage Vg of the transistor TR2. Furthermore, next, in the pixel 23, in a state in which the transistor TR1 is set to an on state and the terminal voltage of the signal level holding capacitor C1 on the transistor TR5 side is thereby set to a voltage Vofs−Vth, the terminal voltage of the signal level holding capacitor C1 on the transistor TR5 side is set to the signal level Vsig of the signal line SIG.
In this case, to be accurate, the gate-source voltage Vgs of the transistor TR2 is represented by the following equation:Vgs=(Cel/Cel+C1+C2)×(Vsig−Vofs)+Vth   (2)where C2 is the capacitance between the gate and the source of the transistor TR2. If the parasitic capacitance Cel of the organic EL element 8 is greater than the capacitance of the signal level holding capacitor C1 and the gate-source capacitance C2 of the transistor TR2, the gate-source voltage Vgs of the transistor TR2 is set to a voltage Vsig+Vth with sufficient accuracy for practical use.
As a result, in the pixel 23, the gate-source voltage Vgs of the transistor TR2 is set to a voltage Vsig+Vth such that a threshold voltage Vth is added to the signal level Vsig of the signal line SIG. As a result, in the display apparatus 21, it is possible to prevent variations in the light-emission luminance due to variations in the threshold voltage Vth, which is one of the characteristics of the transistor TR2.
Next, in the pixel 23, as shown in FIG. 27, during the fixed period T5, the transistor TR3 is set to an on state in a state in which the transistor TR1 is kept set to an on state. As a result, in the pixel 23, the transistor TR2 causes the drain-source current Ids to flow in accordance with the gate-source voltage Vgs resulting from by the potential difference across the ends of the signal level holding capacitor C1. At this time, when the source voltage Vs of the transistor TR2 is smaller than the sum of the threshold voltage Vthel of the organic EL element 8 and the cathode voltage Vcat, and the electric current that flows to the organic EL element 8 is small, as shown in FIG. 28, the source voltage Vs of the transistor TR2 increases gradually from a voltage Vs0 in accordance with the drain-source current Ids of the transistor TR2. The voltage Vs0 is represented by the following equation:Vs0=Vofs−Vth+((C1+C2)/(Cel+C1+C2))×(Vsig−Vofs)   (3)
The rate of increase of the source voltage Vs depends on the mobility μ of the transistor TR2. Cases in which the mobility is large and the mobility is small are indicated by reference characters Vs1 and the Vs2, respectively, and it can be seen that the larger the mobility, the greater the rate of increase of the source voltage Vs.
As a result, in the pixel 23, only during the fixed period T5, in a state in which the transistor TR1 is kept set to an on state, the transistor TR3 is set to an on state, and variations in the light-emission luminance due to variations in the mobility, which is one of the characteristics of the transistor TR2, are prevented.
Thereafter, as shown in FIG. 21, in the pixel 23, the transistor TR1 is set to an off state, and the organic EL element 8 is driven in accordance with the threshold voltage Vth and the gate-source voltage Vgs that is set by correcting the mobility μ. As a result, the source voltage Vs of the transistor TR2 increases as a result of the transistor TR1 being turned off up to a voltage at which the drain-source current Ids of the transistor TR2 flows to the organic EL element 8, and the organic EL element 8 starts to emit light. In consequence, the gate voltage Vg of the transistor TR2 also increases.
According to the configuration shown in FIG. 19, it is possible to prevent a decrease in the light-emission luminance due to changes over time of the organic EL element 8, and it is possible to prevent variations in the light-emission luminance due to variations in the characteristics of the transistor TR2.
However, in the case of the configuration shown in FIG. 19, regarding one pixel 23, it is necessary to provide one signal line SIG, four scanning lines responsive to control signals AZ2 and AZ1 , a driving pulse signal DS, and a writing signal WS, and four wiring patterns of fixed potentials Vcc, Vofs, Vss, and Vcat. Here, the electrode of the fixed potential Vcat is formed on the entire panel by vapor deposition. Therefore, even if scanning lines are used in common at red, blue, and green pixels, wiring patterns of four scanning lines and 3×3 wiring patterns of fixed potentials become necessary with respect to one set of red, blue, and green pixels.
As a result, in a display apparatus of the related art using N-channel transistors, there is a problem in that the number of scanning lines and the number of wiring patterns of fixed potentials become large. When the number of wiring patterns becomes large, it is difficult to efficiently arrange pixels at a high density, and it is difficult to manufacture a high-definition display apparatus with a high yield.